1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to enhanced thermal sensing techniques in semiconductor devices.
2. Description of the Related Art
The fabrication of integrated circuits requires a large number of circuit elements, such as transistors and the like, to be formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors.
The increased packing density of integrated circuits resulting from the reduced device dimensions has given rise to the incorporation of more and more functions into a single semiconductor die. Furthermore, the reduced feature sizes may also be accompanied by reduced switching speeds of the individual transistors, thereby contributing to increased power consumption in MOS circuits, since the reduced switching speeds allow the operation of the transistors at higher switching frequencies, which in turn increases the power consumption of the entire device. In sophisticated applications using densely packed integrated circuits, the heat generation may reach extremely high values due to the dynamic losses caused by the high operating frequency, in combination with a significant static power consumption of highly scaled transistor devices owing to increased leakage currents that may stem from extremely thin gate dielectrics, short channel effects and the like. Therefore, great efforts are being made in order to reduce overall power consumption by restricting the usage of high performance transistors, which usually cause higher heat generation, to performance-critical signal paths in the circuit design, while using less critical devices in other circuit areas. Moreover, appropriate mechanisms may be implemented to operate certain circuit portions “on demand” and control local or global operating conditions, depending on the thermal situation in the semiconductor die. Since external heat management systems may not enable reliable estimation of the die-internal temperature distribution, due to the delayed thermal response of the package of the semiconductor device and the possibly insufficient spatial temperature resolution, respective external concepts may have to be designed to take into consideration these restrictions and provide sufficient operational margins with respect to heat control, or risk overheating and thus possibly destruction of specific critical circuit portions.
Manufacturers of semiconductor products, therefore, increasingly prefer accurate internal temperature measurements that do not substantially depend on external device conditions and dedicated thermal hardware components that may be subject to external tampering, while also avoiding the slow thermal response via the device package. For this purpose, sophisticated heat monitoring regimes may typically be incorporated into the overall design of the integrated circuit, which may enable a device-internal heat management, irrespective of external conditions. Thus, die-internal temperature measurements are typically performed in complex devices, such as CPUs, ASICs and the like, so as to provide device-internal data for controlling the overall operation by reducing operating frequency, switching off respective circuit portions and the like. A respective die-internal heat management system, therefore, relies on accurate temperature measurement. In many approaches, techniques for measuring the die-internal temperature or temperature gradients are accomplished by positioning temperature-sensitive circuits around the die in order to locally determine the temperature. The various temperature measurements may then be combined to provide a global measure of the die temperature, while also allowing a local assessment of the thermal conditions across the die, depending on the distribution of the temperature-sensitive circuits. Hence, the higher a spatial resolution of the measured temperature profile is desired, the more temperature-sensing locations and hence respective sensor circuits are required. The incorporation of a plurality of temperature-sensitive circuits, however, may result in a significant “consumption” of valuable real estate of the semiconductor die, which may typically cause a “competitive” situation during circuit design between actual circuit portions and temperature-sensitive areas. Therefore, frequently, the temperature-sensitive circuit portions are treated with reduced priority compared to the “actual” circuit portions, which may finally result in a circuit design in which the temperature-sensitive circuits are positioned in less than ideal temperature sensing locations. For instance, the design of performance-critical circuit portions of the device that may be operated at higher speed or frequencies may not be compatible with the provisions of sensor elements in these critical areas, for example, due to undesired lengthening of the signal routing and reduction of speed. Hence, although these performance-critical areas usually generate a significantly higher amount of heat, the temperature of such “hot spots” may not be reliably measured, since the temperature-sensitive circuits are positioned by the design constraints at distant locations. Therefore, in this case, damage of the performance-critical areas may occur or respective heat management strategies may be required to take into account the discrepancy of the measurement data and the actual thermal conditions in the performance-critical areas. Similarly, the thermal response of the temperature-sensitive circuits may be affected by the shielding effect of materials and structures that may be provided in the vicinity of the temperature-sensitive circuits. For example, due to the reduced heat dissipation capability of SOI (silicon-on-insulator) devices caused by the buried insulating layer, on which the actual “active” device layer is formed, the corresponding sensing of the momentary temperature in SOI devices is of particular importance, wherein, additionally, the design-dependent positioning of the temperature-sensitive circuits may further contribute to a less efficient overall temperature management in sophisticated SOI devices.
Frequently, for thermal sensing applications, an appropriate diode structure may be used wherein the corresponding characteristic of the diode may permit information to be obtained on the thermal conditions in the vicinity of the diode structure. The sensitivity and the accuracy of the respective measurement data obtained on the basis of the diode structure may significantly depend on the diode characteristic, i.e., on the diode's current/voltage characteristic, which may depend on temperature and other parameters. For thermal sensing applications, it may, therefore, typically be desirable to provide a substantially “ideal” diode characteristic in order to provide the potential for precisely estimating the temperature conditions within the semiconductor device. In SOI devices, a corresponding diode structure, i.e., the respective PN junction, is typically formed in the substrate material located below the buried insulating layer, above which is formed the “active” semiconductor layer used for forming therein the transistor elements. Thus, in addition to the shielding effect of the buried insulating layer, at least some additional process steps may be required, for instance, for etching through the semiconductor layer or a corresponding trench isolation area and through the buried insulating layer in order to expose the crystalline substrate material, thereby contributing to the overall process complexity. Furthermore, the temperature-sensing diodes, in combination with an appropriate evaluation circuit, may also be subject to similar design constraints as described above, irrespective of whether a bulk architecture or an SOI architecture is considered. Hence, currently employed die-internal temperature monitoring mechanisms, although providing significant advantages over external temperature management systems, may suffer from increased die area consumption, reduced proximity to hot spots and thermal isolation of the temperature-sensitive circuits, as will be briefly discussed with reference to FIG. 1.
FIG. 1 schematically illustrates a top view of a semiconductor device 100, which may be provided in the form of a semiconductor die including one or more complex circuits, such as CPU's, memory devices, input/output circuitry and the like. As previously explained, the semiconductor device 100 may have, depending on the overall design criteria, circuit portions of different performance characteristics, such as speed-critical signal paths and the like. Moreover, highly dense circuit areas may be provided, for instance, in the form of memory areas, such as static RAM areas, dynamic RAM areas and the like. For example, a device region 110 may represent an area including a plurality of high performance circuit elements, such as transistor elements having a reduced channel length in combination with a thin gate insulation layer, which may contribute to increased leakage currents, as previously explained. Consequently, upon operation of the device 100, significant heat may be generated in the region 110. Furthermore, an area 111 may represent a device area, in which the overall circuit design may impose tight restrictions with respect to the incorporation of temperature monitoring circuitry and sensors, thereby requiring a certain distance with respect to the high performance region 110. Furthermore, at certain device areas, which are compatible with the overall circuit design, a plurality of temperature-sensitive circuits 120 are typically provided, which include temperature-sensitive elements, such as diodes and the like, in combination with respective support circuitry to receive and evaluate or process temperature-dependent signals. It should be appreciated that the overall structure of the semiconductor device 100 may comprise any appropriate substrate material, such as silicon, and the like, above which is typically formed an appropriate semiconductor layer, such as a silicon-based material in and above which respective circuit elements, such as transistors, capacitors, diodes and the like, are formed in accordance with the technology standard under consideration.
The electrical connection of the individual circuit elements usually may not be accomplished on the same level in which the circuit elements are manufactured, but may require a plurality of additional wiring layers, also referred to as metallization layers, in which highly conductive metal lines which may comprise appropriate metals, such as aluminum, copper and the like, may be routed according to the specified circuit layout. The plurality of metallization layers are interconnected with each other by respective vias, that is, vertical metal-filled contact elements connecting metal lines and metal regions of adjacent stacked metallization layers. Furthermore, a so-called contact structure is provided on the basis of an appropriate dielectric material which encloses the circuit elements, such as the transistors and capacitors and the like, and which acts as an interface to the very first metallization layer. Within the contact structure, respective contact elements or contact plugs are positioned, which connect to respective contact areas of the circuit elements, such as gate electrodes, drain and source regions of transistors and the like. For example, frequently, a combination of silicon nitride, which might act as an etch stop material, followed by silicon dioxide, are common interlayer dielectric materials for the contact structure.
Thus, as previously explained, during operation of the semiconductor device 100, heat is generated in a spatially varying manner, depending on the position of performance-driven circuit portions, such as the device region 110 and the overall configuration of the semiconductor device 100. For instance, in moderately complex systems, in addition to highly complex digital circuits including extremely fast switching transistor elements, in other cases, circuit portions of different power levels may be integrated into the same semiconductor die, thereby also creating a different amount of heat during operation. Since the overall circuit design may not allow positioning of the temperature-sensitive circuits 120 at desired device areas, such as in the vicinity of the performance-driven circuit region 110, without requiring significant design modification, which may be accompanied by performance loss and the like, a reliable detection of the actual temperature in critical device areas may be difficult. Furthermore, coverage of the entire die area, except for less sensitive areas, such as the area 111, may require a plurality of temperature-sensitive circuits 120, which may conventionally consume valuable area in the device layer, i.e., in the semiconductor layer, which also accommodates the actual circuit elements. Hence, in conventional devices, the spatial resolution, as well as the accuracy of temperature-related information, may be lower than is desirable.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.